TinyOS is an open-source operating system designed for wireless embedded sensor
networks. It features a component-based architecture which enables rapid
innovation and implementation while minimizing code size as required by the
severe memory constraints inherent in sensor networks. TinyOS's component
library includes network protocols, distributed services, sensor drivers, and
data acquisition tools -- all of which can be used as-is or be further refined
for a custom application. TinyOS's event-driven execution model enables
fine-grained power management yet allows the scheduling flexibility made
necessary by the unpredictable nature of wireless communication and physical
TinyOS has been ported to over a dozen platforms and numerous sensor boards. A
wide community uses it in simulation to develop and test various algorithms and
protocols. New releases see over 10,000 downloads. Over 500 research groups and
companies are using TinyOS on the Berkeley/Crossbow Motes. Numerous groups are
actively contributing code to the sourceforge site and working together to
establish standard, interoperable network services built from a base of direct
experience and honed through competitive analysis in an open environment.
UPMA (Unified Power Management Architecture):
Energy is an extremely limited resource in in many wireless sensor networks.
While a multitude of different power management strategies have been proposed to
help reduce the amount of energy wasted in these networks, application
developers still face two fundamental challenges when developing systems with
stringent power constraints. First, existing power management strategies are
usually tightly coupled with network protocols and other system functionality.
This monolithic approach has led to standalone solutions that cannot easily be
reused or extended to other applications or platforms. Furthermore, different
power management strategies make different and sometimes even conflicting
assumptions about the rest of the system with which they need to interact.
Without knowledge of which strategies are interoperable with which set of
network protocols, it is difficult for application developers to make informed
decisions as to which strategy is most appropriate for their particular
To address these challenges, we are developing a Unified Power Management
Architecture (UPMA) that supports the flexible composition of different power
management strategies based on application needs. We envision UPMA to consist of
both low level programming interfaces, as well as high level modeling
abstractions. These abstractions will be used to characterize the key properties
of different applications, network protocols, and power management strategies.
Using these properties, configuration tools can be created that match each
application with the most appropriate network protocol and power management
strategy suited to its needs.
On Chip, Networked Logic Analyzer:
When debugging the operation of a Field Programmable Gate Array, it can useful
to see the internal values of logic when certain events occur. A logic analyzer
allows the circuit developer to know the value of internal signals as they
change when an event occurs. Most logic analyzers are standalone systems that
connect to a host.
For this project, a logic analyzer was implemented that can debug FPGA circuits
running on the FPX platform over a network. The circuit consists of
auto-generated VHDL code that records the value of internal FPGA signals as well
as a triggering circuit that waits for an event to occur. Once the event occurs,
all of the signals identified as important are stored to on-chip BlockRAM on
every consecutive clock cycle until memory is full.
The system uses UDP/IP control packets to interface with an external software
client. This software client program controls the operation of the logic
analyzer by sending and receiving UDP/IP packets. It fetches the contents of the
BlockRAMs, and saves the data to a file on the local machine.
This implementation of the logic analyzer lies within the Internet protocol
wrappers on the FPX platform and connects to the circuit device under test. A
front end application allows a developer to select which internal signals they
want to view and when they want to begin data collection. VHDL code for those
signals, as well as the code for the logic analyzer interface is then
automatically generated, and control packets are sent between the logic analyzer
hardware and the control software over the network.